1. Field of Invention
The present invention relates to a shift register, and more particularly, to a shift register used for conducting logic calculations on internal signals to replace clock signals.
2. Description of Related Art
At present, the shift register has been widely used, such as in the source driver and gate driver of the thin film transistor liquid crystal display (TFT LCD) panel. The shift register is formed by connecting a plurality of stage circuits in series. FIG. 1 is a schematic circuit diagram of one of the stage circuits of the conventional shift register.
The stage circuit in FIG. 1 includes inverters I1-I4, three-state inverters T1-T4, and an NAND gate NG. The stage circuit of FIG. 1 receives an input signal IN from the previous stage circuit, and provides an output signal OUT when an output enable signal OE is enabled. The inverter I3 receives a clock signal CK and outputs an inverted clock signal CKB. The clock signals CK and CKB control the three-state inverters T1-T4. The three-state inverter T3 provides the input signal for the next stage circuit.
FIG. 2 is a signal timing diagram when five stage circuits as shown in FIG. 1 are connected in series during operation, wherein IN represents the input signal of the first stage circuit; CK represents the clock signal; OE represents the output enable signal; O1-O5 represent output signals of the first to fifth stage circuits respectively. As shown in FIG. 2, the output signals O1-O5 can be used as the thin film transistor (TFT) ON/OFF signals for five scan lines of the TFT LCD panel.
Each of the three-state inverters in FIG. 1 has the same structure. Taking T1 as an example, FIG. 3 is a schematic circuit diagram of the three-state inverter T1, which includes p-channel metal oxide semiconductor field effect transistors (PMOS transistors) P1 and P2 and n-channel metal oxide semiconductor field effect transistors (NMOS transistors) N1 and N2. The three-state inverter T1 has four end points, i.e., the input end SI, the output end SO, the first control end SC1, and the second control end SC2 respectively. As shown in FIG. 3, the PMOS transistor P1 is electrically connected to the input end SI and the voltage source VDD. The PMOS transistor P2 is electrically connected to the control end SC1, PMOS transistor P1, and the output end SO. The NMOS transistor N1 is electrically connected to the input end SI and the ground end GND. Finally, the NMOS transistor N2 is electrically connected to the control end SC2, NMOS transistor N1, and the output end SO. The output state can be derived from the circuit of the three-state inverter T1 as shown in Table 1.
TABLE 1Output state of three-state inverterEnd pointSISC1SC2SOLogic state0001001111101010
The conventional shift register as mentioned above has the following disadvantages. Due to the coupling of external clock signals, the three-state inverter has an unstable state, thereby resulting in additional electricity consumption. Moreover, the oscillation frequency of external clock signals is much higher than the operation frequency of the shift register. For example, if the above-mentioned shift register is applied to the gate driver of the TFT LCD panel with a resolution of 320×240, the cycle of the clock signals CK and CKB is about 50 us, whereas the operation cycle of the shift register is about 16.6 ms, with a difference of 333 times there-between. The undesirable high-frequency oscillation also results in additional electricity consumption. If the above problems can be eliminated, the electricity consumption of the whole circuit can be reduced.